1. Field of the Invention
The present invention relates to a thermal head driving circuit for driving a thermal head used as a printing unit employed in a facsimile system, a printer or the like.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional one-dot type thermal head driving circuit. A thermal head has the thermal head driving circuit provided so as to correspond to a predetermined number of dots. In the same drawing, designated at numeral 1 is a shift register for shifting input data on the present line in accordance with a clock. The shift register 1 has the number of steps, which correspond to the number of dots for the thermal head. Reference numeral 21 indicates a latch circuit provided in plural form, for taking in data which appears at a tap of the shift register 1 so as to retain it therein. Designated at numeral 31 is a gate signal generator for generating three gate signals GA, GB, GC therefrom. Reference numerals 4a, 4b indicate inverted logical product (hereinafter called "NAND") gates supplied with the outputs of the latch circuit 21 and the gate signals GB, GC. Designated at numeral 51 is a logical product (hereinafter called "AND") gate provided in plural form, for outputting a pulse signal indicative of the state of energization. Further, reference numeral 6 indicates a darlington transistor (driving element) provided in plural form, for driving or energizing each heating or thermal resistor 7 in response to the input pulse signal.
The operation of the thermal head driving circuit will now be described below. The shift register 1 takes in data corresponding to an image signal in response to a clock signal and shifts it (see FIGS. 5(A) and 5(B)). The latch circuit 21 successively takes in data from a tap of the shift register 1, which corresponds to a dot thereof, in response to a latch signal. That is, when the latch signal is input once, the latch circuit 21 shifts the contents of the latch signal and brings data from the shift register 1. As a result, data on the previous line, which is formed of dots thereof, appears at the Q2 terminal and data on a line prior to the previous line, which is formed of dots thereof, appears at the Q3 terminal. Further, data on the present line, which will be printed from now, appears at the Q1 terminal.
The gate signal generator 31 generates the gate signals GA, GB, GC represented in the form of predetermined patterns as illustrated in FIGS. 5(D), 5(E) and 5(F), for example. A signal to be supplied to each thermal resistor 7 is determined by the gate signals, the NAND gates 4a, 4b and the AND gate 51. The darlington transistor 6 drives or energizes the corresponding thermal resistor 7 in response to the determined signal. Each thermal resistor 7 generates heat in proportion to the amount of current which flows therein, and brings a heat-sensitive paper or the like located on the thermal resistor 7 into color development.
A description will now be made of history control of the amount of current supplied to each thermal resistor 7. When a time interval required to energize the thermal resistor 7 is 1 ms as shown in FIG. 2(A), the temperature of the thermal resistor 7 is brought to 300.degree. C. When, on the other hand, the energization of the thermal resistor 7 is repeated in a cycling period corresponding to 2 ms as shown in FIG. 2(B), the temperature of the thermal resistor 7 increases up to 500.degree. C. That is, even if the same amount of current is supplied, the temperature of the thermal resistor 7 at the time of completion of the energization thereof increases if the temperature of the thermal resistor 7 at the start of the energization thereof is high. Thus, a color-developed density becomes high under the condition that the energization of each thermal resistor 7 is effected in a quick repeating cycle unless the energy supplied to the thermal resistor 7 is controlled, thereby causing printing unevenness. It is therefore necessary to control the amount of energy according to the temperature of each thermal resistor at the start of its energization. Described specifically, the control for the energization of each thermal resistor is effected based on a decision made as to whether or not desired data at a line prior to the previous line has been recorded.
This history control is effected in the following manner. That is, it is necessary to recognize the degree of an increase in temperature with respect to each of patterns (recorded conditions of dots on the present line, the previous line and the line prior to the previous line) in order to determine in what manner the energy should be supplied to dots on the present line judging from the recorded conditions of the dots on the previous line and the line prior to the previous line, in other words, the energization should be done with respect to the dots.
FIG. 3 is a simplified graph showing the result of simulation of increases in temperatures with respect to respective patterns at the time that the history control is not effected. In the same drawing, "H" represents that the recording (energization) of dots has been effected, whereas "L" represents that the recording of the dots has not been made. For example, FIG. 3(B) shows the manner in which the recording of dots on the line prior to the previous line is made and the recording of dots on the previous line is not effected. Further, values (each represents the degree of an increase in temperature but is called a point number herein) obtained by normalizing respective temperatures at the time that the energization of the present line has been completed, are shown in the form of numerical values. It is understood that the history control should be effected in such a manner as to provide large energy because the point number is low as illustrated in FIG. 3(A), for example and to provide small energy because the point number is high as shown in FIG. 3(D).
FIG. 4 is a view showing the relationship between the point numbers shown in FIG. 3 and the output data (latch data) which have been latched in the latch circuit 21. As has been already described above, the latch data show whether the dots on the line prior to the previous line, the previous line and the present line are recorded. Now, the number of levels is defined depending on the number of "H". The more the number of "H" produced in a pattern increases, the more the number of levels becomes high. The suitable energized states corresponding to four kinds of patterns shown in FIG. 4 are represented as examples by FIGS. 5(G) through 5(J).
In order to set the suitable amount of current corresponding to the point numbers, the gate signal generator 31 generates the gate signals GA, GB, GC shown in FIGS. 5(D), 5(E) and 5(F). As a result, the outputs of the AND gate 51, which correspond to patterns outputted from the latch circuit 21, are represented as shown in FIGS. 5(G) through 5(J) and hence the amount of current corresponding to the point numbers is set. That is, the pattern (L, L, H) indicative of the low point number is controlled in such a manner that the amount of current increases. On the other hand, the patterns representative of the large point numbers are so controlled that the amount of current decreases. Incidentally, the gate signals GB, GC are identical in pulse width to each other. In the case of patterns which fall under the same level, energization time intervals are identical in total to each other.
Incidentally, as a technique related to the conventional thermal head driving circuit, there is known a thermal head driving device which has been disclosed in Japanese Patent Application Laid-Open Publication No. 64-1560, for example.
The conventional thermal head driving circuit has been constructed as described above. Therefore, when the number of the outputs of the latch circuit 21 is increased to strictly effect the history control, the number of patterns serving as objects to be controlled increases, thereby causing a difficulty in suitably controlling the patterns.
FIG. 6 is a circuit diagram showing a conventional thermal head driving circuit for controlling the energization of each heating or thermal resistor in accordance with a decision made as to whether or not thermal resistors corresponding to adjacent dots generate heat. The same elements of structure as those shown in FIG. 1 are identified by like reference numerals and the description of common elements will therefore be omitted.
In the same drawing, designated at numeral 52 is a logical product (AND) provided in plural form, for outputting a pulse signal indicative of the state of energization. Designated at numeral 82 is an AND gate provided in plural form, which has two input terminals electrically connected to the Q1 terminals of the latch circuits 21 provided adjacent to each other. Reference numeral 92 is an analog switch provided in plural form, which is enabled in response to a signal outputted from the corresponding AND gate 82.
Designated at numeral 102 is a control signal which is input to each analog switch 92 as a predetermined pulse signal.
The operation of the thermal head driving circuit will now be described below. Each latch circuit 21 successively takes in data from a shift register 1 in accordance with a latch signal input from the outside in the same manner as described in the conventional example. As a result, recorded information on the previous line is outputted to the Q2 terminal, whereas recorded information on a line prior to the previous line is outputted to the Q3 terminal. Further, recorded information on the present line appears at the Q1 terminal of each latch circuit 21. However, recorded information, which correspond to adjacent dots, i.e., appear at the Q1 terminals of the respective adjacent latch circuits, are input to their corresponding AND gates 82.
When, on the other hand, the control signal 102 is input to each analog switch 92 in the input timing of the latch signal as shown in FIG. 7 and each analog switch 92 is turned on in response to the output of each AND gate 82, the control signal is input to each gate circuit 52. In this case, as illustrated in FIG. 7, a time interval required to bring the control signal 102 to a conducting state is set so as to be shorter more or less than a time interval required to bring the gate signal GA of the gate signal generator 31 to a conducting state.
When the inputs of any one of the AND gates 82, i.e., the signals of the Q1 terminals of the latch circuits 21 arranged in pairs adjacent to each other are both "H" in level, the analog switch 92 electrically connected to the AND gate 82 is closed so as to supply the control signal 102 to the corresponding gate circuit 51. When, on the other hand, either one of the respective Q1 terminals of the adjacent latch circuits 21 or both Q1 terminals are "L" in level, the corresponding analog switch 92 is turned off, so that the control signal 102 is not supplied to the corresponding gate circuit 51a. Accordingly, each of the gate inputs of the gate circuit 52 is brought to a high impedance.
FIG. 8 shows temperatures on surfaces of adjacent thermal resistors at the time that they have produced heat. Let's now assume that adjacent thermal resistors are respectively represented as 7a, 7b, 7c as shown in FIG. 8(A). When the respective thermal resistors 7a, 7b, 7c are selectively activated under a given condition, heat is generated by the thermal resistor 7b but not produced by the thermal resistors 7a, 7c disposed adjacent to the thermal resistor 7b, for example. In this case, the temperature of the generated heat is 250.degree. C. as shown in FIG. 8(B). When, on the other hand, the heat is produced by the adjacent thermal resistors 7a, 7c, the temperature of the generated heat becomes 280.degree. C. as shown in FIG. 8(D).
Further, when the heat is generated by either one of the thermal resistors 7a and 7c, the temperature of the generated heat is brought to 265.degree. C. as shown in FIG. 8(C). Accordingly, the relative influence of the heat generated by the adjacent thermal resistors on the adjacent thermal resistors can be corrected so as to enable accurate printing by supplying the energy determined by the time required to make the control signal active to each of the thermal resistors 7a, 7b, 7c, thereby making it possible to obtain a well-balanced density for printing under the high-level heat history control.
The conventional thermal head driving circuit is constructed as described above. Therefore, when it is desired to strictly effect the history control, the adjacent data of the Q1 output terminals of the respective latch circuits 21 appear only at one of both ends of the formed circuit. Thus, when the formed circuit is arranged in plural form, each of thermal resistors located at boundaries between the respective adjacent formed circuits for each formed circuit is subjected to heat control different from that effected on other portions, thereby causing a problem that the density control for printing cannot be strictly achieved.